MCK2
MCK3
MCK0
MCK1
MCK2
MCK3
MODT0
MODT1
MODT2
MODT3
MDIC0
MDIC1
LAD00
LAD01
LAD02
LAD03
LAD04
LAD05
LAD06
LAD07
LAD08
LAD09
LAD10
LAD11
LAD12
LAD13
LAD14
LAD15
LAD16
LAD17
LAD18
LAD19
LAD20
Signal
Pin Assignments and Reset States
Table 1. Pins List by Bus (continued)
Signal Description
Clock
Clock
Clock complements
Clock complements
Clock complements
Clock complements
On-die termination
On-die termination
On-die termination
On-die termination
Driver impedance calibration
Driver impedance calibration
Local Bus Controller Interface
Muxed data/address
Muxed data/address
Muxed data/address
Muxed data/address
Muxed data/address
Muxed data/address
Muxed data/address
Muxed data/address
Muxed data/address
Muxed data/address
Muxed data/address
Muxed data/address
Muxed data/address
Muxed data/address
Muxed data/address
Muxed data/address
Muxed data/address
Muxed data/address
Muxed data/address
Muxed data/address
Muxed data/address
Package Pin
Pin Number Type
V8
O
W9
O
W5
O
V5
O
V9
O
W8
O
AD10
O
AG10
O
AD8
O
AF10
O
T6
I/O
AA5
I/O
Power
Supply
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
K26
I/O
BVDD
L26
I/O
BVDD
J26
I/O
BVDD
H25
I/O
BVDD
F25
I/O
BVDD
H24
I/O
BVDD
G24
I/O
BVDD
G23
I/O
BVDD
E23
I/O
BVDD
D23
I/O
BVDD
J22
I/O
BVDD
G22
I/O
BVDD
F19
I/O
BVDD
J18
I/O
BVDD
K18
I/O
BVDD
J17
I/O
BVDD
J25
I/O
BVDD
G25
I/O
BVDD
H23
I/O
BVDD
F22
I/O
BVDD
H22
I/O
BVDD
Notes
—
—
—
—
—
—
—
—
—
—
16
16
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
35
35
35
35
35
P3041 QorIQ Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
13