100315SC 查看數據表（PDF） - Fairchild Semiconductor

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100315SC

Low Skew Quad Clock Driver

Fairchild Semiconductor 

Test Circuit

Note:

Shown for testing CLKIN to CLK1 in the differential mode.

L1, L2, L3 and L4 = equal length 50Ω impedance lines.

All unused inputs and outputs are loaded with 50Ω in parallel with ≤3 pF to GND.

Scope should have 50Ω input terminator internally.

FIGURE 1. AC Test Circuit

Switching Waveforms

FIGURE 2. Propagation Delay, TCLK, CLKSEL to Outputs

FIGURE 3. Propagation Delay, CLKIN/CLKIN to Outputs

FIGURE 4. Transition Times

3

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