MT46V16M8TG-8 查看數據表（PDF） - Micron Technology

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MT46V16M8TG-8

DOUBLE DATA RATE (DDR) SDRAM

Micron Technology 

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

T07

CK#

CK

T1

tLZ(MIN)

T2

T2n

T3

T3n

T4

T4n

T5

T5n

T6

tDQSCK1(MAX)

tDQSCK1(MIN)

tDQSCK1(MAX) tHZ(MAX)

tDQSCK1(MIN)

DQS, or LDQS/UDQS2

tRPRE

tRPST

DQ (Last data valid)

DQ (First data valid)

All DQs collectively3

T2 T2n T3 T3n T4 T4n T5 T5n

T2

T2n

T3

T3n T4

T4n

T5

T5n

T2

T2n T3

T3n T4

T4n T5 T5n

tLZ(MIN)

tAC4(MIN)

tAC4(MAX)

tHZ(MAX)

NOTE: 1. tDQSCK is the DQS output window relative to CK and is the“long term” component of DQS skew.

2. DQs transitioning after DQS transition define tDQSQ window.

3. All DQs must transition by tDQSQ after DQS transitions, regardless of tAC.

4. tAC is the DQ output window relative to CK, and is the“long term” component of DQ skew.

5. tLZ(MIN) and tAC(MIN) are the first valid signal transition.

6. tHZ(MAX ,and tAC(MAX) are the latest valid signal transition.

7. READ command with CL = 2 issued at T0.

Figure 30

Data Output Timing – tAC and tDQSCK

CK#

CK

DQS

DQ

DM

T0

T1

T1n

T2

T2n

T3

tDQSS

tDSH1 tDSS2 tDSH1 tDSS2

tWPRES tWPRE

DI

b

tDQSL tDQSH tWPST

tDS

tDH

DON’T CARE

TRANSITIONING DATA

NOTE: 1. tDSH(MIN) generally occurs during tDQSS(MIN).

2. tDSS(MIN) generally occurs during tDQSS(MAX).

Figure 31

Data Input Timing

128Mb: x4, x8, x16 DDR SDRAM

128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01

58

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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