MT48LC4M4A2 查看數據表（PDF） - Micron Technology

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MT48LC4M4A2

SYNCHRONOUS DRAM

Micron Technology 

A fixed-length READ burst may be followed by, or

truncated with, a WRITE burst (provided that AUTO

PRECHARGE was not activated), and a full-page READ

burst may be truncated by a WRITE burst. The WRITE

burst may be initiated on the clock edge immediately

following the last (or last desired) data element from the

READ burst, provided that I/O contention can be avoided.

In a given system design, there may be a possibility that

the device driving the input data will go Low-Z before the

SDRAM DQs go High-Z. In this case, a single-cycle delay

should occur between the last read data and the WRITE

command.

The DQM input is used to avoid I/O contention, as

shown in Figures 9 and 10. The DQM signal must be

Figure 9

READ to WRITE

T0

T1

T2

T3

T4

CLK

DQM

COMMAND

READ

NOP

NOP

NOP

WRITE

ADDRESS

BANK,

COL n

DQ

tCK

tHZ

BANK,

COL b

DOUT n

DIN b

tDS

NOTE:

A CAS latency of three and a burst of two or more is

used for illustration. The READ command may be to either

bank, and the WRITE command may be to either bank. If a

burst of one is used, then DQM is not required.

16 MEG: x4, x8

SDRAM

asserted (HIGH) at least two clocks prior to the WRITE

command (DQM latency is two clocks for output buffers)

to suppress data-out from the READ. Once the WRITE

command is registered, the DQs will go High-Z (or re-

main High-Z) regardless of the state of the DQM signal.

The DQM signal must be de-asserted prior to the WRITE

command (DQM latency is zero clocks for input buffers)

to ensure that the written data is not masked. Figure 9

shows the case where the clock frequency allows for bus

contention to be avoided without adding a NOP cycle,

and Figure 10 shows the case where the additional NOP

is needed.

Figure 10

READ to WRITE with Extra Clock Cycle

T0

T1

T2

T3

CLK

DQM

T4

T5

COMMAND

READ

NOP

NOP

NOP

NOP

WRITE

ADDRESS

BANK,

COL n

DQ

tHZ

DOUT n

BANK,

COL b

DIN b

tDS

NOTE:

A CAS latency of three is used for illustration. The READ

command may be to either bank, and the WRITE command may be

to either bank.

DON‘T CARE

16 Meg: x4, x8 SDRAM

16MSDRAMx4x8_B.p65 – Rev. 5/98

17

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©1998, Micron Technology, Inc.

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