MT48LC4M4A2 查看數據表（PDF） - Micron Technology

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MT48LC4M4A2

SYNCHRONOUS DRAM

Micron Technology 

FUNCTIONAL BLOCK DIAGRAM

2 Meg x 8 SDRAM

16 MEG: x4, x8

SDRAM

CKE

CLK

CS#

WE#

CAS#

RAS#

CONTROL

LOGIC

ROW-

11 ADDRESS 11

LATCH

2,048

BANK 0

MEMORY

ARRAY

(2,048 x 512 x 8)

512 (x8)

SENSE AMPLIFIERS

I/O GATING

DQM MASK LOGIC

MODE REGISTER

12

9

A0-A10, BA

12

ADDRESS

REGISTER

REFRESH

CONTROLLER

REFRESH 11

COUNTER

ROW-

ADDRESS

MUX

11

ROW-

11 ADDRESS 11

LATCH

512

COLUMN

9

DECODER

512

8

8

SENSE AMPLIFIERS

I/O GATING

DQM MASK LOGIC

512 (x8)

2,048

BANK 1

MEMORY

ARRAY

(2,048 x 512 x 8)

DQM

DATA

OUTPUT

REGISTER

8

DATA

INPUT8

REGISTER

DQ0 -

DQ7

16 Meg: x4, x8 SDRAM

16MSDRAMx4x8_B.p65 – Rev. 5/98

5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©1998, Micron Technology, Inc.

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