AS4LC1M16883C-8EC 查看數據表（PDF） - Austin Semiconductor
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AS4LC1M16883C-8EC Datasheet PDF : 22 Pages
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AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C
1 MEG x 16 DRAM
PRELIMINARY
EDO-PAGE-MODE READ CYCLE
tRASP
tRP
RAS
V
V
IH
IL
tCSH
tPC
tRSH
tCRP
tRCD
tCAS, tCLCH
tCP
tCAS, tCLCH
tCP
tCAS, tCLCH
tCP
CASL/CASH VIH
V IL
,,,,,,,,,,,, ,,, ,,,,,,, , ADDR
V
V
IH
IL
, , WE VIH
, VIL
, , , ,, , DQ VVOOHL
,,,,,,,,, , ,,,,,,,, OE
V IH
V IL
tASR
tRAD
tRAH
ROW
tWRP tWRH
tAR
tACH
tASC
tCAH
COLUMN
tRCS
NOTE 1
OPEN
tCLZ
tAA
tRAC
tCAC
tOE
tOES
tACH
tASC
tCAH
COLUMN
tACH
tASC
tRAL
tCAH
COLUMN
VALID
DATA
tAA
tCPA
tCAC
tCOH
tCLZ
tOEHC
VALID
DATA
tOD
tOEP
tAA
tCPA
tCAC
tOE
tOES
ROW
tRCH
tRRH
tOFF
VALID
DATA
OPEN
tOD
DON’T CARE
UNDEFINED
NOTE:
1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement
?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
SYM
tAA
tACH
tAR
tASC
tASR
tCAC
tCAH
tCAS
tCLCH
tCLZ
tCOH
tCP
tCPA
tCRP
tCSH
tOD
tOE
tOEHC
-6
MIN MAX
30
15
45
0
0
15
10
12 10,000
10
0
3
10
35
5
50
0
15
15
10
-7
MIN MAX
35
15
50
0
0
20
12
13 10,000
10
0
3
10
40
5
55
0
15
20
10
-8
MIN MAX
40
20
60
0
0
20
15
20 10,000
10
0
5
10
40
5
60
0
20
20
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM
tOEP
tOES
tOFF
tPC
tRAC
tRAD
tRAH
tRAL
tRASP
tRCD
tRCH
tRCS
tRP
tRRH
tRSH
tWRH
tWRP
-6
MIN MAX
10
5
3
15
30
60
12
30
10
30
60 100,000
14
45
0
0
40
0
13
10
10
-7
MIN MAX
10
5
3
15
35
70
12 35
10
35
70 100,000
14 50
0
0
50
0
15
10
10
-8
MIN MAX
10
5
0
20
40
80
15 40
10
40
80 100,000
20 60
0
0
60
0
15
10
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AS4LC1M16
REV. 3/97
DS000020
2-106
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
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