AS4LC1M16883C-8EC 查看數據表（PDF） - Austin Semiconductor
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AS4LC1M16883C-8EC Datasheet PDF : 22 Pages
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AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C
1 MEG x 16 DRAM
?R?A/S-ONLY REFRESH CYCLE
PRELIMINARY
tRC
tRAS
tRP
RAS VVIIHL
CASL/CASH
V IH
V IL
,, ,,,, , , ADDR
V IH
V IL
,,,,, ,,,,,,,,,, Q
V
V
OH
OL
, ,,, WE
V
V
IH
IL
tCRP
tASR
tRAH
ROW
tWRP
tWRH
NOTE 1
tRPC
OPEN
tWRP
ROW
,,,, tWRH
CBR REFRESH CYCLE
(Addresses and ?O/E = DON’T CARE)
tRP
tRAS
tRP
tRAS
RAS VVIIHL
tRPC
tCP
tCSR
tCHR
tRPC
tCSR
tCHR
CASL and CASH VVIIHL
DQ
V
V
OH
OL
,,,,,,,,,,,,,,,,, , WE
V
V
IH
IL
tWRP tWRH
NOTE 2
OPEN
tWRP tWRH
, , NOTE:
1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should
implement ?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
2. tWRP and tWRH are for system design reference only. The ?W/E signal is actually a “don’t care” at ?R?A/S time during a CBR
REFRESH. However, ?W/E should be held HIGH at ?R?A/S time during a CBR REFRESH to ensure compatibility with other
DRAMs that require ?W/E HIGH at ?R?A/S time during a CBR REFRESH.
TIMING PARAMETERS
SYM
tASR
tCHR
tCP
tCRP
tCSR
tRAH
-6
MIN MAX
0
10
10
5
5
10
-7
MIN MAX
0
12
10
5
5
10
-8
MIN MAX
0
15
10
5
10
10
UNITS
ns
ns
ns
ns
ns
ns
SYM
tRAS
tRC
tRP
tRPC
tWRH
tWRP
-6
MIN MAX
60 10,000
105
40
5
10
10
-7
MIN MAX
70 10,000
125
50
5
10
10
-8
MIN MAX
80 10,000
150
60
5
10
10
UNITS
ns
ns
ns
ns
ns
ns
AS4LC1M16
REV. 3/97
DS000020
2-111
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
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