73S8014RT 查看數據表（PDF） - Teridian Semiconductor Corporation

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产品描述 (功能)

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73S8014RT

Smart Card Interface

Teridian Semiconductor Corporation 

DS_8014RT_015

73S8014RT Data Sheet

Using 1% external resistors and a parallel resistance of 24K ohms will result in a +/- 6% tolerance in the value of

VDD Fault. The sources of variation due to integrated circuit process variations and mismatches include the

internal reference voltage (less than +/- 1%), the internal comparator hysteresis and offset (less than +/- 1.7% for

part-to-part, processing and environment), the internal resistor value mismatch and value variations (less than

1.8%), and the external resistor values (1%).

If the 2.26V default threshold is used, this pin must be left unconnected.

3.4 Card Power Supply

The card power supply is internally provided by the LDO regulator and controlled by the digital ISO-7816-3

sequencer. Card voltage selection on the 73S8014RT is carried out by the digital inputs CMDVCC% and

CMDVCC#.

3.5 On-Chip Oscillator and Card Clock

The 73S8014RT devices have an on-chip oscillator that can generate the smart card clock using an external

crystal (connected between the pins XTALIN and XTALOUT) to set the oscillator frequency. When the clock

signal is available from another source, it can be connected to the pin XTALIN, and the pin XTALOUT should be

left unconnected.

The card clock frequency may be chosen between 4 different division rates, defined by digital inputs CLKDIV 1

and CLKDIV 2, as per the following table:

CLKDIV1

0

0

1

1

CLKDIV2

0

1

0

1

CLK

1/6 XTALIN

¼ XTALIN

XTALIN

½ XTALIN

Max XTALIN

27MHz

27MHz

20MHz

27MHz

3.6 Activation Sequence

The 73S8014RT smart card interface ICs have an internal 10ms delay on the application of VDD where VDD >

VDDF. No activation is allowed during this 10ms period. The CMDVCC% or CMDVCC# (edge triggered) signals

must then be set low to activate the card. In order to initiate activation, the card must be present; there can be no

VDD fault.

The following steps show the activation sequence and the timing of the card control signals when the system

controller sets CMDVCC% or CMDVCC# low while the RSTIN is low:

- CMDVCC% or CMDVCC# is set low at t0.

- VCC will rise to the selected level and then the internal VCC control circuit checks the presence of VCC at

the end of t1. In normal operation, the voltage VCC to the card becomes valid before t1. If VCC is not valid

at t1, the OFF goes low to report a fault to the system controller, and VCC to the card is shut off.

- Turn I/O to reception mode at t2.

- CLK is applied to the card at t3.

- RST is a copy of RSTIN after t3.

Rev. 1.0

17

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