Philips Semiconductors
Quad 2-input AND gate
Product specification
74AHC08; 74AHCT08
74AHCT family
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS
Tamb (°C)
SYMBOL PARAMETER
OTHER
25
−40 to +85 −40 to +125 UNIT
VCC (V)
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VIH
HIGH-level input
voltage
4.5 to 5.5 2.0 −
−
2.0 −
2.0 −
V
VIL
LOW-level input
voltage
4.5 to 5.5 − −
0.8 − 0.8 − 0.8 V
VOH
HIGH-level output VI = VIH or VIL; 4.5
voltage; all outputs IO = −50 µA
HIGH-level output VI = VIH or VIL; 4.5
voltage
IO = −8.0 mA
VOL
LOW-level output VI = VIH or VIL; 4.5
voltage; all outputs IO = 50 µA
LOW-level output VI = VIH or VIL; 4.5
voltage
IO = 8 mA
II
input leakage
VI = VIH or VIL
5.5
current
4.4 4.5 −
4.4 −
4.4 −
V
3.94 −
−
3.8 −
3.70 −
V
−0
0.1 − 0.1 − 0.1 V
−−
0.36 − 0.44 − 0.55 V
−−
0.1 − 1.0 − 2.0 µA
IOZ
ICC
∆ICC
CI
3-state output
OFF current
VI = VIH or VIL; 5.5
VO = VCC or GND
per input pin;
−−
other inputs at
VCC or GND;
IO = 0
quiescent supply VI = VCC or GND; 5.5
current
IO = 0
−−
additional
VI = VCC − 2.1 V 4.5 to 5.5 − −
quiescent supply other inputs at
current per input VCC or GND;
pin
IO = 0
input capacitance
−
−3
±0.25 − ±2.5 − ±10.0 µA
2.0 −
1.35 −
20 −
1.5 −
40 µA
1.5 mA
10 − 10 − 10 pF
1999 Sep 24
6