Philips Semiconductors
74LV4066
Quad bilateral switches
3. Quick reference data
Table 1: Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns; CL = 15 pF; RL = 1 kΩ.
Symbol Parameter
Conditions
Min Typ Max Unit
tPZL, tPZH
tPLZ, tPHZ
Ci
CS
turn-on time nE to Vos
turn-off time nE to Vos
input capacitance
maximum switch
capacitance
VCC = 3.3 V
VCC = 3.3 V
-
10 -
ns
-
13 -
ns
-
3.5 -
pF
-
8
-
pF
CPD
power dissipation
VCC = 3.3 V
capacitance per switch
[1] [2] -
11 -
pF
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ[(CL + CS) × VCC2 × fo] where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
CS = maximum switch capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ[(CL + CS) × VCC2 × fo] = sum of the outputs.
[2] The condition is VI = GND to VCC.
4. Ordering information
Table 2: Ordering information
Type number Package
Temperature range Name Description
Version
74LV4066N −40 °C to +125 °C DIP14
plastic dual in-line package;
14 leads (300 mil)
SOT27-1
74LV4066D −40 °C to +125 °C SO14
plastic small outline package;
14 leads; body width 3.9 mm
SOT108-1
74LV4066DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; SOT337-1
14 leads; body width 5.3 mm
74LV4066PW −40 °C to +125 °C
TSSOP14 plastic thin shrink small outline
package; 14 leads; body width
4.4 mm
SOT402-1
9397 750 15209
Product data sheet
Rev. 03 — 4 July 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
2 of 23