74LV423 查看數據表（PDF） - Philips Electronics
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74LV423 Datasheet PDF : 16 Pages
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Philips Semiconductors
Dual retriggerable monostable multivibrator
with reset
Preliminary specification
74LV423
AC CHARACTERISTICS (Continued)
GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
SYMBOL
PARAMETER
WAVEFORM
CONDITION
VCC(V)
1.2
LIMITS
–40 to +85 °C
MIN TYP1 MAX
20
1000
–40 to +125 °C
MIN MAX
REXT
External timing
resistor
Figure 6
2.0
5
2.7
5
3.0 to 3.6
2
1000
1000
1000
4.5 to 5.5
2
1000
2.0
CEXT
External timing
capacitor
Figure 63
2.7
3.0 to 3.6
No limits
4.5 to 5.5
NOTES:
1. Unless otherwise stated, all typical values are at Tamb = 25°C.
2. Typical value measured at VCC = 3.3V.
3. Typical value measured at VCC = 5.0V.
4. For other REXT and CEXT combinations see Figure 6.
if CEXT > 10 nF, the next formula is valid:
tW = K x REXT x CEXT (typ.)
where, tW = output pulse width in ns;
REXT = external resistor in kΩ; CEXT = external capacitor in pF;
K = constant = 0.45 for VCC = 5.0V and 0.48 for VCC = 2.0V.
The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is approximately 7 pF.
5. The time to retrigger the monostable multivibrator depends on the values of REXT and CEXT.
The output pulse width will only be extended when the time between the active-going edges of the
trigger pulses meets the minimum retrigger time.
If CEXT > 10 pF, the next formula (at VCC = 5.0V) for the set-up time of a retrigger pulse is valid:
trt = 30 + 0.19R x C-9 + 13 x R1.05 (typ.)
where, trt = retrigger time in ns;
CEXT = external capacitor in pF;
REXT = external resistor in kΩ.
The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is approximately 7 pF.
6. When the device is powered up, initiate the device via a reset pulse, when CEXT < 50pF.
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V.
VOL and VOH are the typical output voltage drop that occur
with the output load.
UNIT
kΩ
pF
nB INPUT
tW
nA INPUT
trt
tW
nQ OUTPUT
tW
tW
tW
SV00139
Figure 2. Output pulse control using retrigger pulse;
nRD = HIGH.
nB INPUT
nRD INPUT
nQ OUTPUT
tW
tW
SV00164
Figure 3. Output pulse control using reset input nRD;
nA = LOW.
1997 Feb 04
8
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