NXP Semiconductors
12. Application information
74LVC169
Presettable synchronous 4-bit up/down binary counter
CP
U/D
PE
D0 D1 D2 D3
PE
U/D
CP
CEP
TC
CET
Q0 Q1 Q2 Q3
D0 D1 D2 D3
PE
U/D
CP
CEP
TC
CET
Q0 Q1 Q2 Q3
least significant
4-bit counter
Fig 14. Synchronous multistage counting scheme
D0 D1 D2 D3
PE
U/D
CP
CEP
TC
CET
Q0 Q1 Q2 Q3
D0 D1 D2 D3
PE
U/D
CP
TC
CEP
CET
Q0 Q1 Q2 Q3
most significant
4-bit counter
001aaa650
74LVC169
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 29 November 2012
© NXP B.V. 2012. All rights reserved.
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