290479-004 查看數據表（PDF） - Intel

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290479-004

PCI, CACHE AND MEMORY CONTROLLER PCMC

Intel 

82434LX 82434NX

If the read cycle causes a cache miss the line

containing the requested data is transferred from

main memory to the cache and to the CPU In the

case of a write-back cache if the cache line fill is

to a sector containing one or more modified lines

the modified lines are written back to main memory

and the new line is brought into the cache For a

modified line write-back operation the PCMC

transfers the modified cache lines to main memory

via a write buffer in the LBX Before writing the last

modified line from the write buffer to main memory

the PCMC updates the first and second level

caches with the new line allowing the CPU access

to the requested data with minimum latency

1 2 1 1 Cache Consistency

The Snoop mechanism in the PCMC ensures data

consistency between cache (both first level and sec-

ond level) and main memory The PCMC monitors

PCI master accesses to main memory and when

needed initiates an inquire (snoop) cycle to the first

and second level caches The snoop mechanism

guarantees that consistent data is always delivered

to both the host CPU and PCI masters

1 2 2 ADDRESS DATA PATHS

Address paths between the CPU cache and PCI

and data paths between the CPU cache PCI and

main memory are supplied by two LBX components

The LBX is a companion component to the PCMC

Together they form a Host PCI bridge The PCMC

(via the PCMC LBX interface signals) controls the

address and data flow through the LBXs Refer to

the LBX data sheet for more details on the address

and data paths

Data is transferred to and from the PCMC internal

registers via the PCMC address lines When the

Host CPU performs a write operation the data is

sent to the LBXs When the PCMC decodes the cy-

cle as an access to one of its internal registers it

asserts AHOLD to the CPU and instructs the LBXs

to copy the data onto the Host address lines When

the PCMC decodes a Host read as an access to a

PCMC internal register it asserts AHOLD to the

CPU The PCMC then places the register data on its

address lines and instructs the LBX to copy the data

on the Host address bus to the Host data bus When

the register data is on the Host data bus the PCMC

negates AHOLD and completes the cycle

1 2 2 1 Read Write Buffers

The LBX provides an interface for the CPU address

and data buses PCI Address Data bus and the

main memory DRAM data bus There are three post-

ed write buffers and one read-prefetch buffers imple-

mented in the LBXs to increase performance and to

maximize concurrency The buffers are

 CPU-to-Main Memory Posted Write Buffer

(4 Qwords)

 CPU-to-PCI Posted Write Buffer (4 Dwords)

 PCI-to-Main Memory Posted Write Buffer (2 x 4

Dwords)

 PCI-to-Main Memory Read Prefetch Buffer (line

buffer 4 Qwords)

Refer to the LBX data sheet for details on the opera-

tion of these buffers

1 2 3 HOST PCI BRIDGE OPERATIONS

The PCMC permits the Host CPU to access devices

on the PCI Bus These accesses can be to PCI I O

space PCI memory space or PCI configuration

space

As a PCI device the PCMC can be either a master

initiating a PCI Bus operation or a target responding

to a PCI Bus operation The PCMC is a PCI Bus

master for Host-to-PCI cycles and a target for PCI-

to-main memory transfers Note that the PCMC does

not permit peripherals to be located on the Host

Bus CPU I O cycles other than to PCMC internal

registers are forwarded to the PCI Bus and PCI Bus

accesses to the Host Bus are not supported

When the CPU initiates a bus cycle to a PCI device

the PCMC becomes a PCI Bus master and trans-

lates the CPU cycle into the appropriate PCI Bus

cycle The Host PCI Posted write buffer in the LBXs

permits the CPU to complete CPU-to-PCI Dword

memory writes in three CPU clocks (1 wait-state)

even if the PCI Bus is currently busy The posted

data is written to the PCI device when the PCI Bus is

available

When a PCI Bus master initiates a main memory ac-

cess the PCMC (and LBXs) become the target of

the PCI Bus cycle and responds to the read write

access During PCI-to-main memory accesses the

PCMC automatically performs cache snoop opera-

tions on the Host Bus when needed to maintain

data consistency

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