AD1837 查看數據表（PDF） - Analog Devices
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AD1837 Datasheet PDF : 24 Pages
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Parameter
TDM256 MODE (Master)
tTBD
BCLK Delay
tFSD
FSTDM Delay
tTABDD
tTDDS
ASDATA Delay
DSDATA1 Setup
tTDDH
DSDATA1 Hold
TDM256 MODE (Slave)
fAB
BCLK Frequency
tTBCH
BCLK High
tTBCL
tTFS
BCLK Low
FSTDM Setup
tTFH
FSTDM Hold
tTBDD
tTDDS
ASDATA Delay
DSDATA1 Setup
tTDDH
DSDATA1 Hold
AUXILIARY INTERFACE
tAXDS
tAXDH
fABP
Slave Mode
AAUXDATA Setup
AAUXDATA Hold
AUXBCLK Frequency
tAXBH
tAXBL
tAXLS
tAXLH
Master Mode
AUXBCLK High
AUXBCLK Low
AUXLRCLK Setup
AUXLRCLK Hold
tAUXBCLK
tAUXLRCLK
AUXLRCLK Delay
AUXLRCLK Delay
Specifications subject to change without notice.
Min
Max
20
5
10
15
15
256 ϫ fS
15
15
10
10
10
15
15
10
10
64 ϫ fS
15
15
10
10
15
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCLK
PD/RST
tMH
tML
tPDR
Figure 1. MCLK and PD/RST Timing
AD1837
Comments
From MCLK Rising
From BCLK Rising
From BCLK Rising
To BCLK Falling
From BCLK Falling
To BCLK Falling
From BCLK Falling
From BCLK Rising
To BCLK Falling
From BCLK Falling
To AUXBCLK Rising
From AUXBCLK Rising
To AUXBCLK Rising
From AUXBCLK Rising
From MCLK Rising
From AUXBCLK Falling
REV. B
–5–
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