AD1838 查看數據表（PDF） - Analog Devices
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AD1838 Datasheet PDF : 24 Pages
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Parameter
TDM256 MODE (Master)
tTBD
BCLK Delay
tFSD
tTABD
tTDDS
FSTDM Delay
ASDATA Delay
DSDATA1 Setup
tTDDH
DSDATA1 Hold
TDM256 MODE (Slave)
fAB
BCLK Frequency
tTBCH
tTBCL
tTFS
BCLK High
BCLK Low
FSTDM Setup
tTFH
tTBDD
tTDDS
FSTDM Hold
ASDATA Delay
DSDATA1 Setup
tTDDH
DSDATA1 Hold
AUXILIARY INTERFACE
tAXDS
tAXDH
tDXD
fABP
Slave Mode
AAUXDATA Setup
AAUXDATA Hold
DAUXDATA Delay
AUXBCLK Frequency
tAXBH
tAXBL
tAXLS
tAXLH
Master Mode
AUXBCLK High
AUXBCLK Low
AUXLRCLK Setup
AUXLRCLK Hold
tAUXLRCLK
tAUXBCLK
AUXLRCLK Delay
AUXBCLK Delay
Specifications subject to change without notice.
Min
15
15
256 ϫ fS
15
15
10
10
15
15
10
10
15
64 ϫ fS
15
15
10
10
5
15
Max
20
5
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AD1838
Comments
From MCLK Rising
From BCLK Rising
From BCLK Rising
To BCLK Falling
From BCLK Falling
To BCLK Falling
From BCLK Falling
From BCLK Rising
To BCLK Falling
From BCLK Falling
To AUXBCLK Rising
From AUXBCLK Rising
From AUXBCLK Falling
To AUXBCLK Rising
From AUXBCLK Rising
From AUXBCLK Falling
From MCLK Rising
MCLK
PD/RST
tMCLK
tMH
tML
tPDR
Figure 1. MCLK and PD/RST Timing
REV. A
–5–
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