AD8381JST 查看數據表（PDF） - Analog Devices
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AD8381JST
Analog Devices
AD8381JST Datasheet PDF : 16 Pages
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AD8381
TIMING CHARACTERISTICS
Parameter
Conditions
Min
Typ
Max
t1 CLK to Data Setup Time
CLK Rise and Fall Time = 5 ns
0
t2 CLK to Data Hold Time
CLK Rise and Fall Time = 5 ns
5
t3 CLK to STSQ Setup Time
CLK Rise and Fall Time = 5 ns
0
t4 CLK to STSQ Hold Time
CLK Rise and Fall Time = 5 ns
5
t5 CLK to XFR Setup Time
CLK Rise and Fall Time = 5 ns
0
t6 CLK to XFR Hold Time
CLK Rise and Fall Time = 5 ns
5
t7 CLK to VID Delay
13.5
15.5
17.5
Unit
ns
ns
ns
ns
ns
ns
ns
DB (0:9)
CLK
STSQ, XFR
–1
0
t1
t2
t3,t5
t4,t6
Figure 1. Timing Requirement E/O = High
DB (0:9)
–1
0
t1
t2
CLK
STSQ
t3
t4
XFR
t5
t6
Figure 2. Timing Requirements E/O = Low
CLK
XFR
t7
VIDx
Figure 3. Output Timing
REV. B
–3–
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