AD9547BCPZ(Rev0) 查看數據表（PDF） - Analog Devices
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AD9547BCPZ Datasheet PDF : 104 Pages
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SERIAL PORT SPECIFICATIONS—SPI MODE
Table 17.
Parameter
CS
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SCLK
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO
As an Input
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
As an Output
Output Logic 1 Voltage
Output Logic 0 Voltage
SDO
Output Logic 1 Voltage
Output Logic 0 Voltage
TIMING
SCLK
Clock Rate, 1/tCLK
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CS to SCLK Setup, tS
CS to SCLK Hold, tC
CS Minimum Pulse Width High
Min
Typ
2.0
0.8
30
110
2
2.0
0.8
1
1
2
2.0
0.8
1
1
2
2.7
2.7
8
12
3
0
10
0
6
AD9547
Max
Unit
Test Conditions/Comments
Internal 30 kΩ pull-up resistor
V
V
μA
μA
pF
Internal 30 kΩ pull-down resistor
V
V
μA
μA
pF
V
V
μA
μA
pF
V
0.4
V
1 mA load current
1 mA load current
V
0.4
V
1 mA load current
1 mA load current
40
MHz
ns
ns
ns
ns
14
ns
ns
ns
ns
Rev. 0 | Page 11 of 104
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