AD9547BCPZ(Rev0) 查看數據表（PDF） - Analog Devices

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AD9547BCPZ
(Rev.:Rev0)

Dual/Quad Input Network Clock Generator/Synchronizer

Analog Devices 

AD9547

Pin No.

47

Input/

Output

I

Pin Type

Differential

input

Mnemonic

REFB

48

I

51

I

52

O

54, 55, 56, 57, I/O

60, 61, 62, 63

EP

O

Differential

input

Logic

3.3 V CMOS

Exposed

pad

REFBB

NC

IRQ

M0, M1, M2, M3,

M4, M5, M6, M7

Exposed pad

Description

Reference B Input. This internally biased input is typically ac-coupled and,

when configured as such, can accept any differential signal with a single-ended

swing of up to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS.

Complementary Reference B Input. Complementary signal to the input provided

on Pin 47. The user can configure this pin as a separate single-ended input.

No Connection. This pin should be left floating.

Interrupt Request Line.

Configurable I/O Pins. These pins are configured under program control.

The exposed pad must be connected to ground (VSS).

Rev. 0 | Page 17 of 104

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