AD9547BCPZ(Rev0) 查看數據表（PDF） - Analog Devices
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AD9547BCPZ Datasheet PDF : 104 Pages
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AD9547
SPECIFICATIONS
Minimum and maximum values apply for the full range of supply voltage and operating temperature variation. Typical values apply for
AVDD3 = DVDD3 = 3.3 V, AVDD = DVDD = 1.8 V, TA = 25°C, IDAC = 20 mA (full scale), unless otherwise noted.
SUPPLY VOLTAGE
Table 1.
Parameter
DVDD3
DVDD
AVDD3
3.3 V Supply (Typical)
1.8 V Supply (Alternative)
AVDD
Min Typ
3.135 3.30
1.71 1.80
3.135 3.30
3.135 3.30
1.71 1.80
1.71 1.80
Max Unit Test Conditions/Comments
3.465 V Pin 7, Pin 58
1.89 V Pin 1, Pin 6, Pin 8, Pin 10, Pin 11, Pin 53, Pin 59, Pin 64
3.465 V Pin 16, Pin 33, Pin 43, Pin 49
3.465 V Pin 25, Pin 31
1.89 V Pin 25, Pin 31
1.89 V Pin 17, Pin 18, Pin 23, Pin 28, Pin 32, Pin 36, Pin 39, Pin 42, Pin 46, Pin 50
SUPPLY CURRENT
The test conditions for the maximum supply current are the same as the test conditions for the All Blocks Running section of Table 3. The
test conditions for the typical supply current are the same as the test conditions for the Typical Configuration section of Table 3.
Table 2.
Parameter
IDVDD3
IDVDD
IAVDD3
3.3 V Supply (Typical)
1.8 V Supply (Alternative)
IAVDD
Min Typ Max Unit Test Conditions/Comments
1.5
3
mA Pin 7, Pin 58
190 215 mA Pin 1, Pin 6, Pin 8, Pin 10, Pin 11, Pin 53, Pin 59, Pin 64
52
70 mA Pin 16, Pin 33, Pin 43, Pin 49
24
55 mA Pin 25, Pin 31
24
55 mA Pin 25, Pin 31
135 150 mA Pin 17, Pin 18, Pin 23, Pin 28, Pin 32, Pin 36, Pin 39, Pin 42, Pin 46, Pin 50
POWER DISSIPATION
Table 3.
Parameter
TYPICAL CONFIGURATION
Min Typ
800
ALL BLOCKS RUNNING
900
FULL POWER-DOWN
13
INCREMENTAL POWER DISSIPATION
SYSCLK PLL Off
Input Reference On
Differential
Single-Ended
Output Distribution Driver On
LVDS
LVPECL
CMOS
−105
7
13
70
75
65
1 fSYSCLK is the frequency at the SYSCLKP and SYSCLKN pins.
2 fS is the sample rate of the output DAC.
3 fDDS is the output frequency of the DDS.
Max Unit Test Conditions/Comments
1100 mW fSYSCLK = 20 MHz1; fS = 1 GHz2; fDDS = 122.88 MHz3; one LVPECL clock
distribution output running at 122.88 MHz (all others powered
down); one input reference running at 100 MHz (all others
powered down)
1250 mW fSYSCLK = 20 MHz1; fS = 1 GHz2; fDDS = 399 MHz3; all clock distribution
outputs configured as LVPECL at 399 MHz; all input references
configured as differential at 100 MHz; fractional-N active (R = 10,
S = 39, U = 9, V = 10)
mW Conditions = typical configuration; no external pull-up or pull-
down resistors
Conditions = typical configuration; table values show the change
in power due to the indicated operation
mW fSYSCLK = 1 GHz1; high frequency direct input mode
mW
mW
mW
mW
mW Single 3.3 V CMOS output with a 10 pF load
Rev. 0 | Page 4 of 104
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