AD9572ACPZLVD 查看數據表（PDF） - Analog Devices

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AD9572ACPZLVD

Fiber Channel/Ethernet Clock Generator IC, 7 Clock Outputs

Analog Devices 

AD9572

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

PLL Characteristics ...................................................................... 3

LVDS Clock Output Jitter............................................................ 4

LVPECL Clock Output Jitter....................................................... 5

CMOS Clock Output Jitter.......................................................... 5

Reference Input............................................................................. 5

Clock Outputs ............................................................................... 6

Timing Characteristics ................................................................ 6

Control Pins .................................................................................. 7

Power.............................................................................................. 7

Crystal Oscillator.......................................................................... 7

Timing Diagrams.............................................................................. 8

Absolute Maximum Ratings............................................................ 9

Thermal Resistance ...................................................................... 9

REVISION HISTORY

/11—Rev. A to Rev. B

Changes to Output Rise Time, tRC2 Parameter and Output Fall

Time, tFC2 Parameter in Table 7....................................................... 6

11/10—Rev. 0 to Rev. A

Changes to Features.......................................................................... 1

Changes to Table 2............................................................................ 4

Changes to Table 3 and Table 4....................................................... 5

Changes to Table 7............................................................................ 6

Added Figure 7 and Figure 8......................................................... 11

Added Figure 14, Figure 15, and Figure 16 ................................. 13

Deleted Original Figure 16 and Figure 19................................... 16

ESD Caution...................................................................................9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 13

Terminology .................................................................................... 15

Theory of Operation ...................................................................... 16

Outputs ........................................................................................ 16

Phase Frequency Detector (PFD) and Charge Pump............ 17

Power Supply............................................................................... 17

CMOS Clock Distribution ........................................................ 17

LVPECL Clock Distribution ..................................................... 18

LVDS Clock Distribution .......................................................... 18

Reference Input........................................................................... 18

Power and Grounding Considerations and Power Supply

Rejection...................................................................................... 19

Outline Dimensions ....................................................................... 20

Ordering Guide .......................................................................... 20

Renumbered Figures Sequentially............................... Throughout

Changes to CMOS Clock Distribution Section.......................... 17

Changes to LVPECL Clock Distribution Section, Added

Figure 23 and Figure 24 ................................................................. 18

Changes to LVDS Clock Distribution Section, Added

Figure 26 .......................................................................................... 18

Changes to Reference Input Section ............................................ 18

Changes to Power and Grounding Considerations and Power

Supply Rejection Section ............................................................... 19

7/09—Revision 0: Initial Version

Rev. B | Page 2 of 20

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