AD9726 查看數據表（PDF） - Analog Devices

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AD9726

16-Bit, 400 MSPS Digital-to-Analog Converter

Analog Devices 

DB0 TO DB15

CLK+/CLK–

tPIPE-BYPASS + tPD-BYPASS

IOUTA OR IOUTB

Figure 5. Data Synchronization Bypass Pipeline Delay

CSB

SCLK

SCLK SET-UP TIME

tCSU SCLK PULSE WIDTH HIGH/LOW TIME

tCPWH

tCPWL

SDIO SET-UP TIME

tDSU

SDIO (SD0)

SDIO HOLD TIME

tDH

SDIO (SD0) VALID TIME

tDV

Figure 6. SPI Timing Diagram

AD9726

Rev. B | Page 7 of 24

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