AD9745-EBZ 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
AD9745-EBZ Datasheet PDF : 28 Pages
| |||
AD9741/AD9743/AD9745/AD9746/AD9747
DIGITAL AND TIMING SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, full-scale digital input, maximum
sample rate, unless otherwise noted.
Table 5. AD9741/AD9743/AD9745/AD9746/AD9747
Parameter
DAC CLOCK INPUTS (CLKP, CLKN)
Differential Peak-to-Peak Voltage
Single-Ended Peak-to-Peak Voltage
Common-Mode Voltage
Input Current
Input Frequency
DATA CLOCK OUTPUT (DCO)
Output Voltage High
Output Voltage Low
Output Current
DAC Clock to Data Clock Output Delay (tDCO)
DATA PORT INPUTS
Input Voltage High
Input Voltage Low
Input Current
Data to DAC Clock Setup Time (tDBS Dual-Port Mode)
Data to DAC Clock Hold Time (tDBH Dual-Port Mode)
DAC Clock to Analog Output Data Latency (Dual-Port Mode)
Data or IQSEL Input to DAC Clock Setup Time (tDBS Single-Port Mode)
Data or IQSEL Input to DAC Clock Hold Time (tDBH Single-Port Mode)
DAC Clock to Analog Output Data Latency (Single-Port Mode)
SERIAL PERIPHERAL INTERFACE
SCLK Frequency (fSCLK)
SCLK Pulse Width High (tPWH)
SCLK Pulse Width Low (tPWL)
CSB to SCLK Setup Time (tS)
CSB to SCLK Hold Time (tH)
SDIO to SCLK Setup Time (tDS)
SDIO to SCLK Hold Time (tDH)
SCLK to SDIO/SDO Data Valid Time (tDV)
RESET Pulse Width High
WAKE-UP TIME AND OUTPUT LATENCY
From DAC Outputs Disabled
From Full Device Power-Down
DAC Clock to Analog Output Latency (Dual-Port Mode)
DAC Clock to Analog Output Latency (Single-Port Mode)
Min
400
300
2.4
2.0
2.0
400
1200
400
1200
10
10
1
0
1
0
10
Typ
800
400
2.2
200
1200
7
8
Max
1600
800
500
1
250
0.4
10
2.8
0.8
1
7
8
40
1
Unit
mV
mV
mV
μA
MHz
V
V
mA
ns
V
V
μA
ps
ps
Cycles
ps
ps
Cycles
MHz
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
Cycles
Cycles
Rev. 0 | Page 7 of 28
Share Link: 