AD9748 查看數據表（PDF） - Analog Devices

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AD9748

8-Bit, 165 MSPS TxDAC® D/A Converter

Analog Devices 

AD9748

Sleep Mode Operation

The AD9748 has a power-down function that turns off the output

current and reduces the supply current to less than 6 mA over

the specified supply range of 2.7 V to 3.6 V and temperature

range. This mode can be activated by applying a logic level 1 to

the SLEEP pin. The SLEEP pin logic threshold is equal to

0.5 ϫ AVDD. This digital input also contains an active pull-down

circuit that ensures that the AD9748 remains enabled if this

input is left disconnected. The AD9748 takes less than 50 ns to

power down and approximately 5 ms to power back up.

POWER DISSIPATION

The power dissipation, PD, of the AD9748 is dependent on

several factors that include the:

∑ Power supply voltages (AVDD, CLKVDD, and DVDD)

∑ Full-scale current output IOUTFS

∑ Update rate fCLOCK

∑ Reconstructed digital input waveform

The power dissipation is directly proportional to the analog supply

current, IAVDD, and the digital supply current, IDVDD. IAVDD is

directly proportional to IOUTFS, as shown in Figure 9, and is insen-

sitive to fCLOCK. Conversely, IDVDD is dependent on both the

digital input waveform, fCLOCK, and digital supply DVDD.

Figure 10 shows IDVDD as a function of full-scale sine wave output

ratios (fOUT/fCLOCK) for various update rates with DVDD = 3.3 V.

35

30

25

20

15

10

5

2

4

6

8 10 12 14 16 18 20

IOUTFS – mA

Figure 9. IAVDD vs. IOUTFS

10

DIFF

9

8

7

6

PECL

5

SE

4

3

2

1

0

0

30

60

90

120

150

180

fCLK

Figure 11. ICLKVDD vs. fCLOCK and Clock Mode

APPLYING THE AD9748

Output Configurations

The following sections illustrate some typical output configura-

tions for the AD9748. Unless otherwise noted, it is assumed that

IOUTFS is set to a nominal 20 mA. For applications requiring the

optimum dynamic performance, a differential output configura-

tion is suggested. A differential output configuration may consist of

either an RF transformer or a differential op amp configuration. The

transformer configuration provides the optimum high frequency

performance and is recommended for any application that allows

ac coupling. The differential op amp configuration is suitable for

applications requiring dc coupling, a bipolar output, signal gain,

and/or level shifting within the bandwidth of the chosen op amp.

A single-ended output is suitable for applications requiring a

unipolar voltage output. A positive unipolar output voltage will

result if IOUTA and/or IOUTB is connected to an appropriately

sized load resistor, RLOAD, referred to ACOM. This configura-

tion may be more suitable for a single-supply system requiring a

dc-coupled, ground referred output voltage. Alternatively, an

amplifier could be configured as an I-V converter, thus converting

IOUTA or IOUTB into a negative unipolar voltage. This con-

figuration provides the best dc linearity since IOUTA or IOUTB

is maintained at a virtual ground.

16

14

165MSPS

12

10

125MSPS

8

6

65MSPS

4

2

0

0.01

0.1

1.0

RATIO – fOUT/fC LOCK

Figure 10. IDVDD vs. Ratio @ DVDD = 3.3 V

REV. 0

–11–

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