AD9780 查看數據表（PDF） - Analog Devices

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AD9780

Dual 12-/14-/16-Bit, LVDS Interface, 500 MSPS DACs

Analog Devices 

Data Sheet

AD9780/AD9781/AD9783

SPI REGISTER MAP

Table 11.

Register Name

SPI Control

Data Control

Power-Down

Setup and Hold

Timing Adjust

Seek

Mix Mode

DAC1 FSC

DAC1 FSC MSBs

AUXDAC1

AUXDAC1 MSB

DAC2 FSC

DAC2 FSC MSBs

AUXDAC2

AUXDAC2 MSB

BIST Control

BIST Result 1 Low

BIST Result 1 High

BIST Result 2 Low

BIST Result 2 High

Hardware Version

Addr

0x00

0x02

0x03

0x04

0x05

0x06

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

Default

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0xF9

0x01

0x00

0x00

0xF9

0x01

0x00

0x00

0x00

0x00

0x00

0x00

0x00

N/A

Bit 7

SDIO_DIR

DATA

PD_DCO

AUX1SGN

AUX2SGN

BISTEN

Bit 6

Bit 5

LSBFIRST RESET

PD_INPT PD_AUX2

SET[3:0]

AUX1DIR

AUX2DIR

BISTRD BISTCLR

VERSION[3:0]

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INVDCO

PD_AUX1 PD_BIAS PD_CLK PD_DAC2 PD_DAC1

HLD[3:0]

SAMP_DLY[4:0]

LVDS low LVDS high SEEK

DAC1MIX[1:0]

DAC2MIX[1:0]

DAC1FSC[7:0]

DAC1FSC[9:8]

AUXDAC1[7:0]

AUXDAC1[9:8]

DAC2FSC[7:0]

DAC2FSC[9:8]

AUXDAC2[7:0]

AUXDAC2[9:8]

BISTRES1[7:0]

BISTRES1[15:8]

BISTRES2[7:0]

BISTRES2[15:8]

DEVICE[3:0]

Rev. B | Page 21 of 32

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