AD9915BCPZ 查看數據表（PDF） - Analog Devices

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AD9915BCPZ

2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC

Analog Devices 

Data Sheet

AD9915

Pin No.

67

82

85

86

Mnemonic

EXT_PWR_DWN

SYNC_CLK

MASTER_RESET

I/O_UPDATE

EPAD

I/O1 Description

I

External Power-Down. Digital input (active high). A high level on this pin initiates the

currently programmed power-down mode.

O Clock Output. Digital output. Many of the digital inputs on the chip, such as I/O_UPDATE,

PS[2:0], and the parallel data port (D0 to D31), must be set up on the rising edge of

this signal.

I

Master Reset. Digital input (active high). Clears all memory elements and sets registers to

default values.

I

Input/Output Update. Digital input (active high). A high on this pin transfers the contents of

the input/output buffers to the corresponding internal registers.

Exposed Pad. The EPAD must be soldered to ground.

1 I means input, O means output, and I/O means input/output.

Rev. F | Page 11 of 47

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