ADL5531(Rev0) 查看數據表（PDF） - Analog Devices

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ADL5531
(Rev.:Rev0)

20 MHz to 500 MHz IF Gain Block

Analog Devices 

ADL5531

BASIC CONNECTIONS

The basic connections for operating the ADL5531 are shown

in Figure 15. The input and output are ac-coupled with 10 nF

(0402) capacitors. DC bias is provided to the amplifier via an

inductor (Coilcraft 1008CS-471XJLC or equivalent) connected

to the RFOUT pin. The bias voltage should be decoupled using

10 nF and 1 μF capacitors.

SOLDERING INFORMATION AND RECOMMENDED

PCB LAND PATTERN

Figure 14 shows the recommended land pattern for ADL5531.

To minimize thermal impedance, the exposed paddle on the

package underside is soldered down to a ground plane. If

multiple ground layers exist, they are stitched together using

vias (a minimum of five vias is recommended). Pin 1, Pin 3,

Pin 4, Pin 6 and Pin 8 can be left unconnected or can be

connected to ground. Connecting these pins to ground slightly

enhances thermal impedance. For more information on land

pattern design and layout, refer to Application Note AN-772, A

Design and Manufacturing Guide for the Lead Frame Chip Scale

Package (LFCSP).

2.03mm

1

8

4

5

0.71mm

1.53mm

Figure 14. Recommended Land Pattern

L1

470nH

ADL5531

VPOS

(TESTLOOP RED)

C5

C6

10nF 1µF

W1

GND

(TESTLOOP BLACK)

RFIN C1

10nF

1 NC

2 RFIN

3 NC

NC 8

RFOUT 7

NC 6

C2

10nF

RFOUT

4 NC

CLIN 5

C3

1nF

NC = NO CONNECT

Figure 15. Basic Connections

Rev. 0 | Page 9 of 12

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