ADP120
OUTLINE DIMENSIONS
2.90 BSC
1.60 BSC
5
4
1
2
3
2.80 BSC
PIN 1
*0.90
0.87
0.84
1.90
BSC
0.95 BSC
0.10 MAX
*1.00 MAX 0.20
0.08
0.50 SEATING
0.30 PLANE
8°
4°
0.60
0°
0.45
0.30
*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 50. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions shown in millimeters
A1 BALL
CORNER
0.860
0.820 SQ
0.780
TOP VIEW
(BALL SIDE DOWN)
0.230
0.200
0.170
0.660
0.600
0.540
SEATING
PLANE
0.40
BALL PITCH
0.280
0.260
0.240
0.050 NOM
COPLANARITY
2
1
A
B
BOTTOM VIEW
(BALL SIDE UP)
Figure 51. 4-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-4-2)
Dimensions shown in millimeters
Rev. A | Page 18 of 20