ADT7482 查看數據表（PDF） - Analog Devices
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ADT7482 Datasheet PDF : 24 Pages
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ADT7482
SPECIFICATIONS
TA = −40°C to +120°C , VDD = 3 V to 3.6 V, unless otherwise noted.
Table 1.
Parameter
Min Typ Max Unit
POWER SUPPLY
Supply Voltage, VDD
3.0 3.30 3.6 V
Average Operating Supply Current, IDD
240 350 μA
5 30 μA
Undervoltage Lockout Threshold
2.55
V
Power-On Reset Threshold
1
2.5 V
TEMPERATURE-TO-DIGITAL CONVERTER
Local Sensor Accuracy
±1 °C
±1.5 °C
±2.5 °C
Resolution
1
°C
Remote Diode Sensor Accuracy
±1 °C
±1.5 °C
±2.5 °C
Resolution
0.25
°C
Remote Sensor Source Current
220
μA
82
μA
13.5
μA
Maximum Series Resistance Cancelled
1.5
kΩ
Conversion Time
71 93 ms
11.5 15 ms
OPEN-DRAIN DIGITAL OUTPUTS
(THERM, ALERT/THERM2)
Test Conditions
0.0625 conversions/sec rate1
Standby mode
VDD input, disables ADC, rising edge
0°C ≤ TA ≤ +70°C
0°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +100°C
0°C
≤
TA
≤
+70°C,
−55°C
≤
T2
DD
≤
+150°C
0°C ≤ TA ≤ +85°C, −55°C ≤ TD2 ≤ +150°C
−40°C ≤ TA ≤ +100°C, −55°C ≤ TD2 ≤ +150°C
High level3
Mid level3
Low level2
Resistance split evenly on D+ and D− lines
From stop bit to conversion complete (all channels) one-shot mode
with averaging switched on
One-shot mode with averaging off (that is, conversion rate = 16, 32,
or 64 conversions per second)
Output Low Voltage, VOL
0.4 V
High Level Output Leakage Current, IOH
0.1 1 μA
SMBus INTERFACE3, 4
Logic Input High Voltage, VIH
2.1
V
SCLK, SDATA
Logic Input Low Voltage, VIL
0.8 V
SCLK, SDATA
Hysteresis
500
mV
SDA Output Low Voltage, VOL
0.4 V
Logic Input Current, IIH, IIL
−1
+1 μA
SMBus Input Capacitance, SCLK, SDATA
5
pF
SMBus Clock Frequency
400 kHz
SMBus Timeout5
25 64 ms
SCLK Falling Edge to SDATA Valid Time
1 μs
IOUT = −6.0 mA
VOUT = VDD
IOUT = −6.0 mA
User programmable
Master clocking in data
1 See Table 11 for conversion rates.
2 Guaranteed by characterization, but not production tested.
3 Guaranteed by design, but not production tested.
4 See the Timing Specifications section for more information.
5 Disabled by default. For details on enabling the SMBus, see the Serial Bus Interface section.
Rev. 0 | Page 3 of 24
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