ADV7322 查看數據表（PDF） - Analog Devices
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ADV7322 Datasheet PDF : 92 Pages
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TIMING DIAGRAMS
CLKIN_A
t9 t10
t12
CONTROL
INPUTS
P_HSYNC,
P_VSYNC,
P_BLANK
Y7–Y0
Y0
Y1
Y2
Y3
Y4
Y5
C7–C0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
t11
t13
CONTROL
OUTPUTS
t14
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
t13 = HD OUTPUT ACCESS TIME
t14 = HD OUTPUT HOLD TIME
Figure 3. HD Only, 4:2:2 Input Mode (Input Mode 010); PS Only, 4:2:2 Input Mode (Input Mode 001)
CLKIN_A
t9 t10
t12
CONTROL
INPUTS
P_HSYNC,
P_VSYNC,
P_BLANK
Y7–Y0
Y0
Y1
Y2
Y3
Y4
Y5
C7–C0
S7–S0
Cb0
Cb1
Cb2
Cb3
Cb4
Cb5
t11
Cr0
Cr1
Cr2
Cr3
Cr4
Cr5
CONTROL
OUTPUTS
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
t13 = HD OUTPUT ACCESS TIME
t14 = HD OUTPUT HOLD TIME
t14
t13
Figure 4. HD Only, 4:4:4 Input Mode (Input Mode 010); PS Only, 4:4:4 Input Mode (Input Mode 001)
ADV7322
Rev. 0 | Page 9 of 92
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