AS7C33128NTD32B 查看數據表（PDF） - Alliance Semiconductor

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AS7C33128NTD32B

3.3V 128K X 32/36 pipeline burst synchronous SRAM

Alliance Semiconductor 

AS7C33128PFS32B

AS7C33128PFS36B

®

Timing waveform of read/write cycle (ADSP Controlled; ADSC High)

CLK

tCYC

tCH

tCL

ADSP

tADSPS

tADSPH

Address

tAS

tAH

A1

A2

A3

GWE

tWS

tWH

CE0, CE2

CE1

ADV

OE

Din

Dout

tADVS

tADVH

tCD

tLZC

Q(A1)

tDS tDH

D(A2)

tHZOE

tLZOE

tOE

Q(A3)

tOH

Q(A3Ý01) Q(A3Ý10) Q(A3Ý11)

DSEL

Read

Q(A1)

Suspend

Read

Q(A1)

Read

Q(A2)

Suspend

Write

D(A 2)

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.

Read

Q(A3)

ADV

Burst

Read

Q(A 3Ý01)

ADV

Burst

Read

Q(A 3Ý10)

ADV

Burst

Read

Q(A 3Ý11)

12/10/04; v.1.7

Alliance Semiconductor

P. 13 of 19

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