AT52BC6402AT 查看數據表（PDF） - Atmel Corporation

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AT52BC6402AT

64-Mbit Flash, 16-Mbit PSRAM (x16 I/O)

Atmel Corporation 

Write Cycle 3 (LB, UB Controlled)

ADDRESS

CS1

CS2

VIH

UB, LB

PSWE

tAS

tAS

tAS

DATA IN HIGH-Z

tWC

tCW

tWR

tAW

tBA

tWP

tDW

DATA VALID

tWR

tDH

Notes: 1. The tBW is specified from the time satisfied both tAS and tWR.

2. Although UB and LB are high state, it’s illegal function to change address both CS and PSWE are in low state.

34 AT52BC6402A(T)

3441B–STKD–11/04

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