AT52BC6402A-70CI 查看數據表（PDF） - Atmel Corporation
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AT52BC6402A-70CI Datasheet PDF : 38 Pages
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Figure 2. Data Polling Algorithm
(Configuration Register = 00)
START
AT52BC6402A(T)
Figure 3. Data Polling Algorithm
(Configuration Register = 01)
START
Read I/O7 - I/O0
Addr = VA
I/O7 = Data?
YES
NO
NO
I/O3, I/O5 = 1?
YES
Read I/O7 - I/O0
Addr = VA
I/O7 = Data?
YES
NO
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Program/Erase
Operation
Successful,
Device in
Read Mode
Read I/O7 - I/O0
Addr = VA
NO
I/O7 = 1?
YES
NO
I/O3, I/O5 = 1?
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
Note:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
Notes:
1. VA = Valid address for programming. During a sec-
tor erase operation, a valid address is any sector
address within the sector being erased. During
chip erase, a valid address is any non-protected
sector address.
2. I/O7 should be rechecked even if I/O5 = “1”
because I/O7 may change simultaneously with
I/O5.
9
3441B–STKD–11/04
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