AT88SC153-09PT-00 查看數據表（PDF） - Atmel Corporation

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AT88SC153-09PT-00

3 x 64 x 8 Secure Memory with Authentication

Atmel Corporation 

Timing Diagrams

Figure 15. Bus Timing (SCL: Serial Clock; SDA: Serial Data I/O)

Figure 16. Synchronous Answer-to-reset Timing

Figure 17. Write Cycle (SCL: Serial Clock; SDA: Serial Data I/O)

SCL

SDA

8th BIT

WORD n

ACK

tWR

STOP

CONDITION

START

CONDITION

Note: The write cycle time tWR is the time from valid stop condition of a write sequence to the

end of the internal clear/write cycle.

18 AT88SC153

1016D–SMEM–04/04

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