BD4153FV,BD4153EFV
●Reference data
V3AUX
V3
CP#
SYSR
Fig.1 System Stand-by→Active
(Card)
V3AUX
V3
CP#
SYSR
Fig.4 PCI Card Assert/DeAssert
(Stand-by)
V3 RISETIME
10000
1000
100
10
1
0.1
0.01 1.00E-10
1.00E-09
1.00E-08
CSS_V3 (F)
1.00E-07 1.00E-06
Fig.7 V3 RISETIME
PERST#
V3
SS_V3
Logic Input(CP#)
Fig.10 V3 Start up
(Card Assert)
V3AUX
V3
CP#
SYSR
Fig.2 System Active⇔Stand-by
(Card)
V3AUX
V3
CP#
SYSR
Fig.5 Card Assert/DeAssert
(Active)
V3 rise propagation delay TIME
10000
1000
100
10
1
0.1
1.00E-10
0.01
1.00E-09
1.00E-08
CSS_V3 (F)
1.00E-07 1.00E-06
Fig.8 V3 rise
Propagation delay TIME
PERST#
V3
SS_V3
Logic Input(EN)
Fig.11 V3 Wave Form
(Shut down→Active)
Technical Note
V3AUX
V3
CP#
SYSR
Fig. System Stand-by⇔Active
(No Card)
CPUSB#
V3
V3AUX
PERST#
Fig.6 USB Card Assert/ DeAssert
(Active)
PERST#
V3
SS_V3
Logic Input(SYSR)
Fig.9 V3 Start up
(Stand-by→Active)
V3AUX RISE TIME
10000
1000
100
10
1
0.1
0.011.00E-10
1.00E-09
1.00E-08
1.00E-07
CSS_V3AUX (F)
Fig.12 V3AUX
RISE TIME
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4/17
2010.04 - Rev.B