BD8179MUV 查看數據表（PDF） - ROHM Semiconductor
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BD8179MUV Datasheet PDF : 13 Pages
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BD8179MUV
Technical Note
(5) Design of the Feedback Resistor Constant
Refer to the following equation to set the feedback resistor. As the setting range, 10 kΩ to 330 kΩ is recommended. If the
resistor is set lower than a 10 kΩ, it causes the reduction of power efficiency. If it is set more than 330 kΩ, the offset
voltage becomes larger by the input bias current 0.4 µA(Typ.) in the internal error amplifier.
VMAIN =
R1 + R2
R2
1.233
[V]
Vo
R1
R2
Reference voltage 1.233 V
23
FB
＋ERR
－
(6) Positive-side Charge Pump Settings
BD8179MUV incorporates a charge pump controller, thus making it possible to generate stable gate voltage.
The output voltage is determined by the following formula. As the setting range, 10 kΩ to 330 kΩ is recommended. If the
resistor is set lower than a 10kΩ, it causes the reduction of power efficiency. If it is set more than 330 kΩ, the offset
voltage becomes larger by the input bias current 0.4 µA (Typ.) in the internal error amp.
VGON =
R3 + R4
R4
1.25 [V]
VGON
C3 R3
1000 pF to 4700 pF
R4
Reference voltage 1.25 V
25
FBP
＋ERR
－
In order to prevent output voltage overshooting, add capacitor C3 in parallel with R3. The recommended capacitance is
1000 pF to 4700 pF. If a capacitor outside this range is inserted, the output voltage may oscillate.
By connecting capacitance to the DEL, a rising delay time can be set for the positive-side charge pump.
The delay time is determined by the following formula.
Delay time of charge pump block t DELAY
t DELAY = ( CDEL 1.25 )/5 µA [s]
Where, CDEL is the external capacitance.
(7) Negative-side Charge Pump Settings
BD8179MUV incorporates a charge pump controller for negative voltage, thus making it possible to generate stable gate voltage.
The output voltage is determined by the following formula. As the setting range, 10 kΩ to 330 kΩ is recommended. If the
resistor is set lower than a 10 kΩ, it causes the reduction of power efficiency. If it is set more than 330 kΩ, the offset
voltage becomes larger by the input bias current 0.4 µA (Typ.) in the internal error amp.
VGOFF
0.25 V
VGOFF =
-
R5
R6
1.0 + 0.25 V
[V]
C5 R5
1000 pF to 4700 pF
R6
－
ERR
27
＋
FBN
2
REF
1.25 V
The delay time is internally fixed at 200 us.
In order to prevent output voltage overshooting, insert capacitor C5 in parallel with R5. The recommended capacitance is
1000 pF to 4700 pF. If a capacitor outside this range is inserted, the output voltage may oscillate.
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10/12
2009.07 - Rev.B
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