BU7242SF-E2 查看數據表（PDF） - ROHM Semiconductor
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BU7242SF-E2
ROHM Semiconductor
BU7242SF-E2 Datasheet PDF : 37 Pages
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BU7261/BU7261S family, BU7241/BU7241S family, BU7295/BU7295S family, BU7275/BU7275S family
BU7262/BU7262S family, BU7242/BU7242S family, BU7264/BU7264S family, BU7244/BU7244S family Technical Note
●Test circuit 1 NULL method
Parameter
VF
S1
Input Offset Voltage
VF1 ON
Large Signal Voltage Gain
VF2
VF3
ON
Common-mode Rejection Ratio
VF4
(Input Common-mode Voltage Range) VF5
ON
Power Supply Rejection Ratio
VF6
VF7
ON
VDD, VSS, EK, Vicm Unit: [V]
S2
S3 VDD VSS EK Vicm Calculation
ON OFF
3
0
-1.5
3
1
ON
ON
3
0
-0.5
-2.5
1.5
2
ON OFF
3
0
-1.5
0
3
3
ON
OFF
1.8
5.5
0
-0.9
0
4
－Calculation－
1. Input Offset Voltage (Vio)
Vio = |VF1| [V]
1+Rf/Rs
2. Large Signal Voltage Gain (Av)
Av = 20Log 2×(1+Rf/Rs) [dB]
|VF2-VF3|
3. Common-mode Rejection Ratio (CMRR)
CMRR = 20Log 1.8×(1+Rf/Rs) [dB]
|VF4-VF5|
4. Power Supply Rejection Ratio (PSRR)
PSRR = 20Log 3.7×(1+Rf/Rs) [dB]
|VF6-VF7|
0.1[µF]
Vicm
SW1
VDD
RS=50[Ω]
Ri=1[MΩ]
0.015[µF] 0.015[µF]
RS=50[Ω] Ri=1[MΩ]
DUT
50[kΩ]
SW2
VSS
Rf=50[kΩ]
500[kΩ]
EK
Vo
500[kΩ]
SW3
RL
VRL
1000[pF]
0.01[µF]
15[V]
LL
VF
-15[V]
Fig.185 Test circuit 1 (one channel only)
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27/36
2010.12 - Rev.A
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