74AVC16373DGG 查看數據表（PDF） - Philips Electronics
零件编号
产品描述 (功能)
生产厂家
74AVC16373DGG Datasheet PDF : 16 Pages
| |||
Philips Semiconductors
16-bit D-type transparent latch; 3-state
Objective specification
74AVC16373;
74AVCH16373
FEATURES
• Wide supply voltage range of 1.2 V to
3.6 V
• Complies with JEDEC standard
no. 8-1A/5/7
• CMOS low power consumption
• Input/Output tolerant up to 3.6 V
• DCO (Dynamic Controlled Output)
Circuit dynamically changes output
impedance, resulting in noise
reduction without speed degradation
• Low inductance multiple VCC and
GND pins for minimize noise and
ground bounce.
• All data inputs have bushold.
(only 74AVCH16373)
• Power off disables 74AVC16373;
74AVCH16373 outputs, permitting
Live Insertion.
DESCRIPTION
The 74AVC(H)16373 is a 16-bit D-type
transparent latch featuring separate D-type
inputs for each latch and 3-State outputs
for bus oriented applications. Incorporates
bushold data inputs which eliminate the
need for external pull-up resistors to hold
unused inputs. One latch enable(LE) input
and one enable OE are provided per 8-bit
section.
This product is designed to have an
extremely fast propagation delay and a
minimum amount of power consumption.
To ensure the high-impedance output state
during power up or power down, OEn
should be tied to VCC through a pullup
resistor (Live insertion).
A Dynamic Controlled Output (DCO)
circuitry is implemented to support
termination line drive during transient. See
graphs at this page for typical curves.
The 74AVCH16373 consist of 2 sections of
eight D-type transparant latches with
3-State true outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.0 ns; CL = 30 pF.
SYMBOL PARAMETER
CONDITIONS TYPICAL UNIT
tPHL/ tPLH propagation delay VCC = 1.8 V
1.6
ns
Dn to Qn
VCC = 2.5 V
1.3
ns
VCC = 3.3 V
1.1
ns
tPHL/ tPLH propagation delay VCC = 1.8 V(3)
1.7
ns
LE to Qn
VCC = 2.5 V(3)
1.4
ns
VCC = 3.3 V(3)
1.2
ns
CI
input capacitance
5.0
pF
CPD
power dissipation notes 1 and 2
capacitance per
outputs enabled 22
pF
buffer
output disabled 5
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
∑ (CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC.
3. For type with bushold.
0
-50
-100
1.8V
-150
-200
-250
-300
2.5V
3.3V
PMOS
-350
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-350
-300
-250
-200
-150
-100
-50
0
0
VOH (V) OUTPUT VOLTAGE
3.3V
1.8V
2.5V
NMOS
0.5
1.0
1.5
2.0
2.5
VOL (V) OUTPUT VOLTAGE
3.0
3.5
1998 Dec 11
2
Share Link: 