CMX881 查看數據表（PDF） - CML Microsystems Plc
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CMX881 Datasheet PDF : 59 Pages
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PMR Signalling Processor
Operating Characteristics
For the following conditions unless otherwise specified:
External components as recommended in Figure 2.
Maximum load on digital outputs = 30pF.
Xtal Frequency = 18.432MHz ±0.01% (100ppm).
VDD = 2.7V to 5.5V; Tamb = −40°C to +85°C.
Reference Signal Level = 308mV rms at 1kHz with VDD = 3V.
Signal to Noise Ratio (SNR) in bit rate bandwidth.
Input stage gain = 0dB.
Output stage attenuation = 0dB.
DC Parameters
Notes Min.
Supply Current
IDD(D) (VDD = 3.0V)
IDD(A) (VDD = 3.0V)
IDD(D) (All Power-saved) (VDD = 3.0V)
IDD(A) (All Power-saved) (VDD = 3.0V)
C-BUS Interface
Input Logic ‘1’
Input Logic ‘0’
Input Leakage Current (Logic ‘1’ or ‘0’)
Input Capacitance
Output Logic ‘1’
(IOH = 120µA)
Output Logic ‘0’
(IOL = 360µA)
“Off” State Leakage Current
IRQN
(Vout = VDD(D))
REPLY_DATA (output HiZ)
21
21
21
21
70%
−1.0
-
90%
−1.0
−1.0
CLOCK_OUT
Output Logic ‘1’
Output Logic ‘0’
(IOH = 120µA)
(IOH = 1mA)
(IOL = 360µA)
(IOL = -1.5mA)
CLOCK/XTAL
22
Input Logic ‘1’
Input Logic ‘0’
Input current (Vin = VDD)
Input current (Vin = VSS)
VBIAS
23
Output voltage offset wrt VDD/2 (IOL < 1µA)
Output impedance
90%
80%
70%
−40
-2%
Typ.
4.5
1.0
2.0
2.0
22
CMX881
Max.
Unit
8.0
mA
2.0
mA
10
µA
10
µA
VDD
30%
VDD
1.0
µA
7.5
pF
VDD
10%
VDD
10
µA
1.0
µA
1.0
µA
10%
15%
VDD
VDD
VDD
VDD
VDD
30%
VDD
40
µA
µA
+2%
VDD
kΩ
Notes: 21
22
23
Not including any current drawn from the device pins by external circuitry.
Characteristics when driving the CLOCK/XTAL pin with an external clock source.
Applies when utilising VBIAS to provide a reference voltage to other parts of the
system. When using VBIAS as a reference, VBIAS must be buffered. VBIAS must
always be decoupled with a capacitor as shown in Figure 2.
2004 CML Microsystems Plc
49
D/881/7
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