CS5101A 查看數據表（PDF） - Cirrus Logic

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CS5101A

16-bit, 100 kSps / 20 kSps A/D Converters

Cirrus Logic 

CS5101A CS5102A

fine-charge until HOLD goes low. To get an accu-

rate sample using the CS5101A, at least 750 ns of

coarse-charge, followed by 1.125 µs of fine-charge

is required before initiating a conversion. If coarse

charge is not invoked, then up to 25 µs should be

allowed after a step change input for proper acqui-

sition. To get an accurate sample using the

CS5102A, at least 3.75 µs of coarse-charge, fol-

lowed by 5.625 µs of fine-charge is required before

initiating a conversion (see Figure 4). If coarse

charge is not invoked, then up to 125 µs should be

allowed after a step change input for proper acqui-

sition. The CRS/FIN pin must be low prior to HOLD

becoming active and be held low during conver-

sion.

CLKIN

CR S/FIN

In te rn a l

S ta tu s

Conv.

TRK1 or

TRK2

M in: 750 ns*

3.75 µs**

Coarse

M in: 1.125 µs*

6 clk

5.625 µs**

Fine C hg. Coarse

2 clk

Fine Chg.

Conv.

HOLD

* Applies to 5101A

** Applies to 5102A

Figure 4. Coarse/Fine Charge Control

4.3 Master Clock

The CS5101A and CS5102A can operate either

from an externally-supplied master clock, or from

their own crystal oscillator (with a crystal). To en-

able the internal crystal oscillator, simply tie a crys-

tal across the XOUT and CLKIN pins and add 2

capacitors and a resistor, as shown on the system

connection diagram in Figure 9.

Calibration and conversion times directly scale to

the master clock frequency. The CS5101A can op-

erate with clock or crystal frequencies up to 9.216

MHz (8.0 MHz in FRN mode). This allows maxi-

mum throughput of up to 50 kSps per channel in

dual-channel operation, or 100 kSps in a single-

channel configuration. The CS5102A can operate

with clock or crystal frequencies up to 2.0 MHz (1.6

MHz in FRN mode). This allows maximum

throughput of up to 10 kSps per channel in dual-

channel operation, or 20 kSps in a single channel

configuration. For 16-bit performance a 1.6 MHz

clock is recommended. This 1.6 MHz clock yields

a maximum throughput of 20 kSps in a single-

channel configuration.

4.4 Asynchronous Sampling

Considerations

When HOLD goes low, the analog sample is cap-

tured immediately. The HOLD signal is latched by

the next falling edge of CLKIN, and conversion

then starts on the subsequent rising edge. If HOLD

is asynchronous to CLKIN, then there will be a 1.5-

CLKIN-cycle uncertainty as to when conversion

starts. Considering the CS5101A with an 8 MHz

CLKIN, with a 100 kHz HOLD signal, then this 1.5-

CLKIN uncertainty will result in a 1.5-CLKIN-period

possible reduction in fine charge time for the next

conversion.

This reduced fine charge time will be less than the

minimum specification. If the CLKIN frequency is

increased slightly (for example, to 8.192 MHz) then

sufficient fine charge time will always occur. The

maximum frequency for CLKIN is specified at

9.216 MHz. It is recommended that for asynchro-

nous operation at 100 kSps, CLKIN should be be-

tween 8.192 MHz and 9.216 MHz.

18

DS45F6

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