CY7C017AV 查看數據表（PDF） - Cypress Semiconductor

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CY7C017AV

3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM

Cypress Semiconductor 

Switching Waveforms

Read Cycle No. 1 (Either Port Address Access)[24, 25, 26]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

Read Cycle No. 2 (Either Port CE/OE Access)[24, 27, 28]

CE

OE

DATA OUT

ICC

CURRENT

ISB

tACE

tDOE

tLZOE

tLZCE

tPU

Read Cycle No. 3 (Either Port)[24, 26, 27, 28]

tRC

ADDRESS

tAA

CY7C138AV/144AV/006AV

CY7C139AV/145AV/016AV

CY7C007AV/017AV

DATA VALID

tOHA

tHZCE

tHZOE

DATA VALID

tPD

tOHA

CE

DATA OUT

tLZCE

tABE

tACE

tLZCE

Notes:

24. R/W is HIGH for read cycles.

25. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads.

26. OE = VIL.

27. Address valid prior to or coincident with CE transition LOW.

28. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.

tHZCE

Document #: 38-06051 Rev. *C

Page 10 of 20

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