CY7C017A-15(2010) 查看數據表（PDF） - Cypress Semiconductor

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CY7C017A-15
(Rev.:2010)

32 K/16 K × 8, 16 K × 9 Dual-Port Static RAM

Cypress Semiconductor 

CY7C006A/CY7C007A

CY7C016A/CY7C017A

Switching Waveforms (continued)

Busy Timing Diagram No. 1 (CE Arbitration)[44]

CELValid First:

ADDRESS L,R

ADDRESS MATCH

CEL

CER

BUSYR

CER Valid First:

ADDRESS L,R

tPS

tBLC

tBHC

ADDRESS MATCH

CER

CE L

BUSYL

tPS

tBLC

tBHC

Busy Timing Diagram No. 2 (Address Arbitration)[44]

Left Address Valid First:

ADDRESS L

ADDRESSR

tRC or tWC

ADDRESS MATCH

tPS

ADDRESS MISMATCH

BUSY R

tBLA

tBHA

Right Address Valid First:

ADDRESSR

ADDRESSL

BUSY L

tRC or tWC

ADDRESS MATCH

tPS

tBLA

ADDRESS MISMATCH

tBHA

Note

44. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.

Document Number: 38-06045 Rev. *F

Page 15 of 22

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