CY7C025E 查看數據表（PDF） - Cypress Semiconductor
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CY7C025E Datasheet PDF : 22 Pages
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CY7C024E, CY7C0241E
CY7C025E, CY7C0251E
Logic Block Diagram
L
L
L
OE L
R/WR
UBR
LBR
CE
R
OE R
[10]
I/O 8L – I/O 15L
I/O
0L
–
I/O
[9]
7L
[6]
BUSYL
(CY7C025E/0251E) A12L
A11L
A0L
R/W L
SEM L
INT L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
CE L
OE L
UB L
LB L
INTERRUPT
SEMAPHORE
ARBITRATION
M/S
CE R
OE R
UB R
LB R
I/O8R – I/O15R[3]
I/O 0R– I/O 7R [2]
[1]
BUSYR
A12R (CY7C025E/0251E)
A11R
A0R
R/W R
SEM R
INTR
Notes
1. BUSY is an output in master mode and an input in slave mode.
2. I/O0 –I/O8 on the CY7C0241E/CY7C0251E.
3. I/O9 –I/O17 on the CY7C0241E/CY7C0251E.
Document Number: 001-62932 Rev. *B
Page 2 of 22
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