CY7C1360C-250AXC 查看數據表（PDF） - Cypress Semiconductor

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CY7C1360C-250AXC

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

Cypress Semiconductor 

PRELIMINARY

CY7C1360C

CY7C1362C

Logic Block Diagram – CY7C1362C (512K x 18)

A0, A1, A

MODE

ADV

CLK

ADSC

ADSP

BWB

ADDRESS

REGISTER

2 A[1:0]

BURST Q1

COUNTER AND

LOGIC

CLR

Q0

DQB,DQPB

WRITE REGISTER

DQB,DQPB

WRITE DRIVER

DQA,DQPA

BWA

WRITE REGISTER

BWE

DQA,DQPA

WRITE DRIVER

GW

CE1

CE2

ENABLE

REGISTER

PIPELINED

ENABLE

CE3

OE

MEMORY

ARRAY

SENSE

OUTPUT

AMPS

REGISTERS

OUTPUT

BUFFERS

E

DQs

DQPA

DQPB

INPUT

REGISTERS

ZZ

SLEEP

CONTROL

Selection Guide

250 MHz

200 MHz

166 MHz

Maximum Access Time

2.8

3.0

3.5

Maximum Operating Current

250

220

180

Maximum CMOS Standby Current

30

30

30

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Unit

ns

mA

mA

Document #: 38-05540 Rev. *C

Page 2 of 31

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