CY7C63001-SC 查看數據表（PDF） - Cypress Semiconductor

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CY7C63001-SC

Universal Serial Bus Microcontroller

Cypress Semiconductor 

PRELIMINARY

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

TABLE OF FIGURES

Figure 5-1. Program Memory Space ................................................................................................... 8

Figure 5-2. Data Memory Space .......................................................................................................... 9

Figure 5-3. Status and Control Register (Address 0xFF) ................................................................ 10

Figure 5-4. Watch Dog Reset (WDR) ................................................................................................. 11

Figure 5-5. Timer Register (Address 0x23)....................................................................................... 11

Figure 5-6. Timer Block Diagram....................................................................................................... 12

Figure 5-7. Port 0 Data Register (Address 0x00) ............................................................................. 12

Figure 5-8. Port 1 Data Register (Address 0x01) ............................................................................. 12

Figure 5-9. Block Diagram of an I/O Line.......................................................................................... 13

Figure 5-10. Port 0 Pull-Up Register (Address 0x08)....................................................................... 13

Figure 5-11. Port 1 Pull-Up Register (Address 0x09)....................................................................... 13

Figure 5-12. Port Isink Register for One GPIO Line......................................................................... 14

Figure 5-13. The Cext Register (Address 0x22) ............................................................................... 14

Figure 5-14. Clock Oscillator On-chip Circuit .................................................................................. 14

Figure 5-15. Global Interrupt Enable Register (Address 0x20)....................................................... 15

Figure 5-16. Interrupt Controller Logic Block Diagram ................................................................... 15

Figure 5-17. Port 0 Interrupt Enable Register (Address 0x04)........................................................ 16

Figure 5-18. Port 1 Interrupt Enable Register (Address 0x05)........................................................ 16

Figure 5-19. GPIO Interrupt Logic Block Diagram ........................................................................... 17

Figure 5-20. USB Device Address Register (Address 0x12) ........................................................... 18

Figure 5-21. USB End Point 0 RX Register (Address 0x14) ............................................................ 18

Figure 5-22. USB Engine Response to SETUP and OUT transactions on End Point 0 ................ 19

Figure 5-23. USB End Point 0 TX Configuration Register (Address 0x10) .................................... 19

Figure 5-24. USB End Point 1 TX Configuration Register (Address 0x11) .................................... 20

Figure 5-25. USB Status and Control Register (Address 0x13)...................................................... 20

Figure 8-1. Clock Timing .................................................................................................................... 24

Figure 8-2. USB Data Signal Timing.................................................................................................. 24

TABLE OF TABLES

Table 5-1. I/O Register Summary......................................................................................................... 9

Table 5-2. Output Control Truth Table ..............................................................................................13

Table 5-3. Interrupt Vector Assignments..........................................................................................16

Table 5-4. Instruction Set Map ...........................................................................................................21

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