CY8C52(2011_03) 查看數據表（PDF） - Cypress Semiconductor
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CY8C52 Datasheet PDF : 94 Pages
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PRELIMINARY
PSoC® 5: CY8C52 Family Datasheet
Table 14-1. Acronyms Used in this Document (continued)
Acronym
PICU
PLA
PLD
PLL
PMDD
POR
PRES
PRS
PS
PSoC®
PSRR
PWM
RAM
RISC
RMS
RTC
RTL
RTR
RX
SAR
SC/CT
SCL
SDA
S/H
SIO
SNR
SOC
SOF
Description
port interrupt control unit
programmable logic array
programmable logic device, see also PAL
phase-locked loop
package material declaration data sheet
power-on reset
precise power-on reset
pseudo random sequence
port read data register
Programmable System-on-Chip™
power supply rejection ratio
pulse-width modulator
random-access memory
reduced-instruction-set computing
root-mean-square
real-time clock
register transfer language
remote transmission request
receive
successive approximation register
switched capacitor/continuous time
I2C serial clock
I2C serial data
sample and hold
special input/output, GPIO with advanced
features. See GPIO.
signal-to-noise ratio
start of conversion
start of frame
Table 14-1. Acronyms Used in this Document (continued)
Acronym
SPI
SR
SRAM
SRES
SWD
SWV
TD
THD
TIA
TRM
TTL
TX
UART
Description
Serial Peripheral Interface, a communications
protocol
slew rate
static random access memory
software reset
serial wire debug, a test protocol
single-wire viewer
transaction descriptor, see also DMA
total harmonic distortion
transimpedance amplifier
technical reference manual
transistor-transistor logic
transmit
Universal Asynchronous Transmitter Receiver, a
communications protocol
UDB
USB
USBIO
VDAC
WDT
universal digital block
Universal Serial Bus
USB input/output, PSoC pins used to connect to
a USB port
voltage DAC, see also DAC, IDAC
watchdog timer
WOL
WRES
XRES
write once latch, see also NVL
watchdog timer reset
external reset I/O pin
XTAL
crystal
15. Reference Documents
PSoC® 3, PSoC® 5 Architecture TRM
PSoC® 5 Registers TRM
Document Number: 001-66236 Rev. **
Page 92 of 94
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