CY8C52(2011_03) 查看數據表（PDF） - Cypress Semiconductor
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CY8C52 Datasheet PDF : 94 Pages
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PRELIMINARY
PSoC® 5: CY8C52 Family Datasheet
Figure 2-2. 100-pin TQFP Part Pinout
(TRACEDATA[1], GPIO) P2[5] 1
(TRACEDATA[2], GPIO) P2[6] 2
(TRACEDATA[3], GPIO) P2[7] 3
(I2C0: SCL, SIO) P12[4] 4
(I2C0: SDA, SIO) P12[5] 5
(GPIO) P6[4] 6
(GPIO) P6[5] 7
(GPIO) P6[6] 8
(GPIO) P6[7] 9
Vssb 10
Ind 11
Vboost 12
Vbat 13
Vssd 14
XRES 15
(GPIO) P5[0] 16
(GPIO) P5[1] 17
(GPIO) P5[2] 18
(GPIO) P5[3] 19
(TMS, SWDIO, GPIO) P1[0] 20
(TCK, SWDCK, GPIO) P1[1] 21
(configurable XRES, GPIO) P1[2] 22
(TDO, SWV, GPIO) P1[3] 23
(TDI, GPIO) P1[4] 24
(nTRST, GPIO) P1[5] 25
Lines show Vddio
to I/O supply
association
TQFP
75 Vddio0
74 P0[3] (GPIO, OpAmp0-/Extref0)
73 P0[2] (GPIO, OpAmp0+)
72 P0[1] (GPIO, OpAmp0out)
71 P0[0] (GPIO, OpAmp2out)
70 P4[1] (GPIO)
69 P4[0] (GPIO)
68 P12[3] (SIO)
67 P12[2] (SIO)
66 Vssd
65 Vdda
64 Vssa
63 Vcca
62 NC
61 NC
60 NC
59 NC
58 NC
57 NC
56 P15[3] (GPIO, kHz XTAL: Xi)
55 P15[2] (GPIO, kHz XTAL: Xo)
54 P12[1] (SIO, I2C1: SDA)
53 P12[0] (SIO, I2C1: SCL)
52 P3[7] (GPIO, OpAmp3out)
51 P3[6] (GPIO, OpAmp1out)
Figure 2-3 and Figure 2-4 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog
performance on a 2-layer board.
The two pins labeled Vddd must be connected together.
The two pins labeled Vccd must be connected together, with capacitance added, as shown in Figure 2-3 and Power System on
page 21. The trace between the two Vccd pins should be as short as possible.
The two pins labeled Vssd must be connected together.
For information on circuit board layout issues for mixed signals, refer to the application note, AN57821 - Mixed Signal Circuit Board
Layout Considerations for PSoC® 3 and PSoC 5.
Note
5. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-66236 Rev. **
Page 6 of 94
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