CY8C5248PVI-028 查看數據表（PDF） - Cypress Semiconductor

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CY8C5248PVI-028

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

EM_ Clock

EM_ CEn

EM_ Addr

EM_ OEn

EM_ Data

EM_ ADSCn

PRELIMINARY

PSoC®5: CY8C52 Family Data Sheet

Figure 11-3. Synchronous Read Cycle Timing

Tcp

Tceld

Tcehd

Taddrv

Toeld

Address

Toehd

Taddriv

Tadscld

Tds

Tdh

Data

Tadschd

Table 11-45. Synchronous Read Cycle Specifications

Parameter

Description

T

EMIF Clock period

Tcp

EM_Clock Period

Tceld

EM_Clock low to EM_CEn low

Tcehd

EM_Clock high to EM_CEn high

Taddrv EM_Clock low to EM_Addr valid

Taddriv EM_Clock high to EM_Addr invalid

Toeld

EM_Clock low to EM_OEn low

Toehd

EM_Clock high to EM_OEn high

Tds

Data valid before EM_Clock high

Tdh

Data valid after EM_Clock high

Tadscld EM_clock low to EM_ADSCn low

Tadschd EM_clock high to EM_ADSCn high

Conditions

Min

Typ

30.3

-

30.3

-

-

T/2 - 2

-

-

-

T/2 - 2

-

-

-

T+2

-

20

-

2

-

-

-

T/2 - 2

-

Max

Units

-

ns

-

ns

5

ns

-

ns

5

ns

-

ns

5

ns

-

ns

-

ns

-

ns

5

ns

-

ns

Document Number: 001-55034 Rev. *A

Page 72 of 85

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