CYRF69213(2007) 查看數據表（PDF） - Cypress Semiconductor

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CYRF69213
(Rev.:2007)

Programmable Radio on Chip Low Power

Cypress Semiconductor 

CYRF69213

Figure 9. Clock Block Diagram

CPUCLK

SEL

CLK_EXT

CLK_24MHz

MUX

SCALE (divide by 2n,

n = 0-5,7)

CPU_CLK

EXT

24 MHz

MUX

CLK_USB

SEL

SCALE

SEL SCALE OUT

0

X 12 MHz

0

X 12 MHz

1

1

EXT/2

1

1

EXT

LP OSC

32 KHz

CLK_32

KHz

Clock Architecture Description

The CYRF69213 clock selection circuitry allows the selection

of independent clocks for the CPU, USB, Interval Timers, and

Capture Timers.

The CPU clock, CPUCLK, can be sourced from the external

crystal oscillator or the Internal 24-MHz Oscillator. The

selected clock source can optionally be divided by 2n where n

is 0–5,7 (see Table 34).

USBCLK, which must be 12 MHz for the USB SIE to function

properly, can be sourced by the Internal 24-MHz Oscillator or

the external crystal oscillator. An optional divide-by-two allows

the use of the 24-MHz source.

The Interval Timer clock (ITMRCLK), can be sourced from the

external crystal oscillator, the Internal 24-MHz Oscillator, the

Internal 32-KHz Low-power Oscillator, or from the timer

capture clock (TCAPCLK). A programmable prescaler of 1, 2,

3, 4 then divides the selected source.

The Timer Capture clock (TCAPCLK) can be sourced from the

external crystal oscillator, Internal 24-MHz Oscillator, or the

Internal 32-KHz Low-power Oscillator.

When it is not being used by the external crystal oscillator, the

CLKOUT pin can be driven from one of many sources. This is

used for test and can also be used in some applications. The

sources that can drive the CLKOUT are:

• CLKIN after the optional EFTB filter

• Internal 24-MHz Oscillator

• Internal 32-KHz Low-power Oscillator

• CPUCLK after the programmable divider

Document #: 001-07552 Rev. *B

Page 21 of 85

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