DS1254 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS1254

2M x 8 NV SRAM with Phantom Clock

Dallas Semiconductor -> Maxim Integrated 

DS1254

RAM READ MODE

The DS1254 executes a read cycle whenever WE is inactive (high) and CE is active (low). The unique

address specified by the 21 address inputs (A0–A20) defines which of the 2MB of data is to be accessed.

Valid data will be available to the eight data-output drivers within tACC (access time) after the last address

input is stable, providing that CE and OE access times and states are also satisfied. If OE and CE access

times are not satisfied, then data access must be measured from the later occurring signal ( CE or OE ) and

the limiting parameter is either tCO for CE or tOE for OE rather than address access.

RAM WRITE MODE

The DS1254 is in the write mode whenever WE and CE are in their active (low) state after address inputs

are stable. The later occurring falling edge of CE or WE will determine the start of the write cycle. The

write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid

throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before

another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to

avoid bus contention. However, if the output bus has been enabled ( CE and OE active), then WE will

disable the outputs in tODW from its falling edge.

DATA RETENTION MODE

The device is fully accessible and data can be written and read only when VCC is greater than VPF.

However, when VCC falls below the power-fail point, VPF (point at which write protection occurs), the

internal clock registers and SRAM are blocked from any access. When VCC falls below VBAT, device

power is switched from the VCC to VBAT. RTC operation and SRAM data are maintained from the battery

until VCC is returned to nominal levels. All signals must be powered down when VCC is powered down.

PHANTOM CLOCK OPERATION

Communication with the phantom clock is established by pattern recognition on a serial bit stream of

64 bits that must be matched by executing 64 consecutive write cycles containing the proper data on

DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.

After recognition is established, the next 64 read or write cycles either extract or update data in the

phantom clock, and memory access is inhibited.

Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control

of chip enable ( CE ), output enable ( OE ), and write enable ( WE ). Initially, a read cycle to any memory

location using the CE and OE control of the phantom clock starts the pattern-recognition sequence by

moving a pointer to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are

executed using the CE and WE signals of the device. These 64 write cycles are used only to gain access to

the phantom clock. Therefore, any address within the first 512kB of memory, (00h to 7FFFFh) is

acceptable. However, the write cycles generated to gain access to the phantom clock are also writing data

to a location in the memory. The preferred way to manage this requirement is to set aside just one address

location in memory as a phantom clock scratch pad. When the first write cycle is executed, it is compared

to bit 0 of the 64-bit comparison register. If a match is found, the pointer increments to the next location

of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not

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