EL1508CL 查看數據表（PDF） - Intersil

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EL1508CL

Differential DSL Line Driver

Intersil 

EL1508

combination of the quiescent power and the output stage

power when driving the line:

Pd = Pquiescent + Poutput-stage

Pd = VS × IQ + (VS – 2 × VOUT-RMS ) × IOUT-RMS

In the full power mode and with 6.8k RADJ registers, the

EL1508 consumes typically 7mA quiescent current and still

able to maintain very low distortion. The distortion results are

shown in typical performance section of the data sheet.

When driving a load, a large portion (about 50%) of the

quiescent current becomes output load current:

Pd = 12 × (7mA × 50% ) + (12V – 3.16 ) × 31.6mA × 2

where:

Pd = 598mW

The θJA requirement needs to be calculated. This is done

using the equation:

ΘJA

=

T----J---U-----N----C----T-----–----T----A----M-----B--

PDISS

where:

TJUNCT is the maximum die temperature (150°C)

TAMB is the maximum ambient temperature (85°C)

PDISS is the dissipation calculated above

θJA is the junction to ambient thermal resistance for the

package when mounted on the PCB

ΘJA

=

1----5---0-----–-----8---5--

598 m W

=

108 ° C / W

PCB Layout Considerations for QFN and SOIC

Packages

The EL1508 die is packaged in three different thermally-

efficient packages: a 20 Ld SOIC (0.300”), a 16 Ld SOIC

(0.150”), and a 24 Ld QFN. The 16 Ld SOIC has the same

external dimensions as a standard 0.150” width SOIC

package, but has the center four leads (two per side)

internally-fused for heat transfer purposes. Both packages

can use PCB surface metal vias areas and internal ground

planes, to spread heat away from the package. The larger

the PCB area the lower the junction temperature of the

device will be. In XDSL applications, multiple layer circuit

boards with internal ground plane are generally used. 13 mil

vias are recommended to connect the metal area under the

device with the internal ground plane. Examples of the PCB

layouts are shown in the figures below that result in thermal

resistance θJA of 37°C/W for the QFN package and 47°C/W

for the SOIC package. The thermal resistance is obtained

with the EL1508CL and CS demo boards. The demo board

is a 4-layer board built with 2oz. copper and has a dimension

of 4in2. Note, the user must follow the thermal layout

guideline to achieve these results. In addition to lower

thermal resistance, the QFN package exhibits much lower

2nd harmonic distortion.

A separate Application Note for the QFN package and layout

recommendations is also available.

TX+

+ VS+ RT

FROM

-

VS-

RF

10 0.22µF TXFR 1:1

AFE

2RG

3k

100

1.5kΩ

TX-

VS+

+

RT

-

VS-

10

0.22µF

RF

3k

FIGURE 44. TYPICAL ADSL CO LINE DRIVER

IMPLEMENTATION

TOP (24 LD QFN)

INTERNAL GROUND PLANE (24 LD QFN)

14

FN7014.5

March 26, 2007

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